1. Field of the Invention
The present invention relates to a cache memory device to be placed between a main memory and a processor in a computer, for the sake of facilitating high speed accesses and, more particularly, to such a cache memory device capable of speeding up data-write processes.
2. Description of the Background Art
As the ability and speed of a processor (or CPU) in a computer improve with advances in research on Architecture and VLSI, it becomes clear that to take full advantage of a high speed processor either the speed of a memory device for access from the processor needs to be improved or the number of such accesses needs to be reduced. To implement such an improvement calls for a high speed memory with a large capacity, but, in general, a high speed memory (static memory) has a small capacity and is expensive, whereas a large capacity memory (dynamic memory) is slow.
As a solution to this situation, the use of a cache memory has been developed. The cache memory is a high speed, small capacity type memory placed between a slow, large capacity main memory and a processor in a system, and those data which are frequently accessed are stored in a data storing part (referred hereafter as a data memory) of the cache memory, in addition to being in the main memory, so that the system as a whole effectively speeds up.
In such a system, there is provided a hit/miss detector for preventing incorrect data processing, which detects the presence in the cache memory of a datum with an address to which the processor attempts to make access (referred hereafter as a processor address), by producing a hit or a miss signal according to present datum or absent datum (referred also as cache-hit or cache-miss in the following), respectively.
This hit/miss detector usually utilizes another memory called a tag memory which stores addresses from the main memory of data stored in the data memory of the cache memory (referred hereafter as a memory addresses), and a comparator which compares the processor address with the memory addresses in the tag memory to decide the presence or the absence in the cache memory of the datum with the address in question. Thus, in this type of system, making access from the processor takes a reading from the tag memory and a comparison at the comparator, which requires extra time for the comparison to be carried out, compared with direct access to the data.
Conventionally, this situation is improved by adopting a so called delayed-wait method in which the data in the data memory are fed to the processor for the data-read process regardless of cache-hit or cache-miss, and information concerning cache-hit or cache-miss, i.e., whether the fed data are right ones or not, is given at the next cycle of the process.
A timing chart for this type of data-read process is shown in FIG. 1, which shows a case in which the data-read at the process cycle 0 is cache-hit, whereas the data-read at the process cycle 1 is cache-miss.
More specifically, at the process cycle 0, an access to an address 0 is made by the processor, and in the same process cycle 0, data 0 having a corresponding location in the data memory are read out and fed to the processor. But, in this process cycle 0, the hit/miss signal is uncertain as it is not specified yet by the hit/miss detector. The hit/miss signal is subsequently ascertained as hit at the next process cycle 1, thereby confirming the legitimacy of the data 0 and the address 0. In effect, the required data 0 are taken to the processor in the process cycle 0 alone.
On the other hand, at the process cycle 1, another access to another address 1 is made and data x having a corresponding location in the data memory are fed. As this is a cache-miss which is indicated by the hit/miss signal being a miss at the next process cycle 2, the data x taken to the processor are regarded as illegitimate and the processor waits until the hit/miss signal becomes a hit. Meanwhile, correct data 1 are read from the main memory, and fed to the processor at the process cycle n, and as the hit/miss signal becomes a hit at the process cycle (n+1), the processor resumes the subsequent operation.
Thus, by this delayed-wait method, it is possible to complete the data-read process in one process cycle so long as the access is a cache-hit, thereby speeding up the data-read process.
However, the same has not been the case for the data-write process conventionally. This is because a data-write process in a conventional cache memory device can be carried out only after the cache-hit or cache-miss of the access is determined, as the data-write process takes place on memories such as a data memory and a main memory.
Especially, a so called copy-back (also called direct mapping) type cache memory has the following problem. In a copy-back type cache memory, a data-write process is carried out in the cache memory only, and not in the main memory. The data in the main memory is changed only when the data in the cache memory is replaced by the other data with different addresses. In other words, only the data in the cache memory are kept up to date. Consequently, it is necessary to ensure that the data-write process is carried out with respect to a correct address. Otherwise, the currently correct data in the cache memory may be destroyed by overwriting incorrect data, and then only the obsolete data in the main memory are left. Thus, it is particularly important for a conventional copy-back type cache memory device to carry out the data-write process only after the cache-hit or cache-miss of the access is determined.
A timing chart for this type of data-write process is shown in FIG. 2, which shows a case in which the data-write at the process cycles 0 and 1 is a cache-hit, whereas the data-write at the process cycles 2 and 3 is a cache-miss. More specifically, at the process cycle 0 an access to an address 0 is made by the processor with data 0 as a write-data. But, since the hit/miss signal at this process cycle 0 is uncertain, a write command is off. Only at the process cycle 1 at which the hit/miss signal becomes a hit does the write command change to on, and the data-write process is carried out. So a single data-write process takes two process cycles. On the contrary, the data-write process for another address 1 with data 1 as a write-data at the process cycles 2 and 3 is cache-miss, so the write command remains the off at both process cycles and data-write process does not take place.
Thus, in a conventional cache memory device, the data-write process requires at least two process cycle, one for determining a cache-hit or a cache-miss, and another for carrying out data-write, which is twice as long as what is required for the data-read process.